1. Technical Field
The present invention relates to time delay compensation circuits, and more particularly, to a time delay compensation circuit comprising delay cells having various unit time delays.
2. Discussion of the Related Art
In an I/O interface where data is transmitted in synchronization with a clock signal, as the load on a data bus is increased and the frequency of the clock signal becomes higher, it becomes more difficult to correctly synchronize the clock signal with the data. That is, the data needs to be correctly synchronized with an edge or the center of the clock signal.
A time delay compensation circuit is typically employed to achieve synchronization. Examples of time delay compensation circuits include a phase-locked loop and a delay-locked loop, which are closed loops, and a synchronous mirror delay (SMD), which is an open loop.
While the phase-locked loop and the delay-locked loop are both accurate, they need a locking time of 100 cycles or more to complete synchronization. Conversely, while SMD is not as accurate as the phase-locked loop or the delay-locked loop, synchronization can be completed with a locking time of only 2 cycles.
FIG. 1 is a block diagram of a typical delay-locked loop.
A delay compensation method of the typical delay locked-loop 100 will be described now. A phase detector 120 detects a phase difference between an external clock signal EXCLK and a feedback clock signal FEDCLK and generates an error control signal ERRS corresponding to the phase difference.
A filter unit 130 increases or decreases the number of delay cells operating in a delay line 110, which includes several delay cells (not shown), in response to the error control signal ERRS. The delay line 110 delays the external clock signal EXCLK by a certain time and outputs the external clock signal EXCLK as an output clock signal OCLK. The output clock signal OCLK is transmitted as a feedback clock signal FEDCLK to the phase detector 120.
The delay line 110 includes a plurality of delay cells each having a fixed unit time delay. When a long time delay is needed, many delay cells are selected from the delay line 110, and when a short time delay is needed, relatively few delay cells are selected.
The number of delay cells selected to operate in the delay line 110 is closely related to the frequency of the external clock signal EXCLK. When the frequency of the external clock signal EXCLK is great, a long time delay is needed. Thus, many delay cells are used. However, when the frequency of the external clock signal EXCLK is small, a few delay cells are used.
FIG. 2 is a block diagram of a typical synchronous mirror delay (SMD).
Referring to FIG. 2, the typical SMD 200 comprises a buffer 210 that receives an external clock signal EXCLK, a delay monitor circuit 220, a forward delay array 230 that delays the external clock signal EXCLK forward, a mirror control circuit 240, a backward delay array 250 that delays an output of the mirror control circuit 240 backward, and a clock driver 260.
The forward delay array 230 delays the external clock signal EXCLK forward from a predetermined edge of the external clock signal EXCLK to the next edge using the delay cells. The backward delay array 250 delays the external clock signal EXCLK backward from a predetermined edge of the external clock signal EXCLK to a previous edge using the delay cells. Thus, the synchronization is completed in only two cycles.
FIG. 3 illustrates delay cells in the delay line 110 shown in FIG. 1 and in the forward delay array 230 and the backward delay array 250 shown in FIG. 2.
As illustrated in FIG. 3, the delay line of the typical delay-locked loop, or the forward delay array or the backward delay array of the typical SMD, includes serially connected delay cells having an identical unit time delay tD.
When a cycle of the external clock signal EXCLK is tCK, tCK/tD delay cells are needed to compensate for the phase difference between the external clock signal EXCLK and the output clock signal OCLK.
The time delay compensation circuit, such as the delay-locked loop 100 shown in FIG. 1, or the synchronous mirror delay 200 shown in FIG. 2, causes the following problem. To obtain synchronization with an external clock signal having a low frequency, a large number of delay cells, connected in series, may be needed. However, the delay-locked loop or the synchronous mirror delay can only obtain synchronization with an external clock signal within a limited frequency range due to layout restrictions.
Consequently, if a single delay cell is designed to have a long unit time delay, when an external clock signal with a low frequency is input, the time delay compensation circuit can operate normally. However, serious jitter may be caused due to quantization error after the synchronization because synchronization using delay cells having a long unit time delay is less precise than synchronization using delay cells having a short unit time delay.
Conversely, when a single delay cell has a short unit time delay, the jitter can be reduced. However, a comparatively large number of delay cells needs to be used in the time delay compensation circuit.
Therefore, a need exists for a time delay compensation circuit for synchronizing an external clock signal using relatively few delay cells as compared to a conventional time delay compensation circuit.